1. Field of the Invention
This invention relates generally to data processing systems and more specifically to a data processing system having a cache memory.
2. Description of the Prior Art
A cache memory is a small, high speed memory that maintains a copy of previously selected portions of main memory for faster re-access to instructions and data. The computer system, using a cache memory, appears the same as a conventional system with main memory, except that execution of programs is noticeably faster because the cache memory is synchronized with the processor and eliminates the longer bus transmission and access times associated with main memory.
Cache memories are well known in the art and were developed from an evaluation of the statistics of program behavior. More specifically, the principle of program locality states that programs have a tendency to make the most accesses or entries in the neighborhood of locations accessed in the recent past. Programs typically execute instructions in straight lines comprising small loops or subroutines, with the next few accesses or entries probably occurring within a few word locations ahead of or behind the current location. A cache exploits this type of program behavior by keeping copies of the recently used words.
A cache, then, is a small block of high speed memory utilized in conjunction with main memory. All of the data is stored in main memory and a copy of some of the data is stored in cache. If, for the most part, the needed data is in the cache or fast memory, the program will execute quickly, slowing down only when accesses must be made to main memory. The primary concern then is instruction execution speed. This is determined by the speed of the cache memory and the main memory and the frequency with which memory references find the data in the cache (hits) by comparison with the number of times the data is not in cache (misses).
The testing of a cache memory is a different task due to its transparency to the programmer and due to the fact that it is an integral part of the operating system. Part of the problem is solved by the utilization of a hit status register which monitors and stores the outputs of hit/miss circuitry providing a record of whether recent memory references were accessed in cache or in the main memory.
However, because the cache is a fundamental part of the operating system, it must be used to diagnose itself. In the past, this has forced the diagnostic programmer to execute instructions out of a possibly bad cache. Typically, in order to avoid this problem, the programmer had the ability to disable or "force misses" in all of the cache memory. However, this hardward feature did not realistically solve the problem for a small, economical system having a relatively small cache (such as, for example 1024 words) since the diagnostic programmer is forced to straight line code his test so that no instructions are executed out of cache. In terms of a small, economic system having a limited amount of main memory, and in light of all the different tests and patterns which must be performed to diagnose each location in the cache, the program size becomes exorbitant. More specifically, there is typically insufficient storage space in the main memory to economically accommodate this procedure.
Thus, as data processing systems become smaller and more economical, an inexpensive and effective method is needed to diagnose the cache and which permits the disablement of a faulty portion of the cache while the remainder of the cache continues to operate as an integral part of the data processing system.